I. Field of the Invention
The present invention relates to computer systems. More particularly, the present invention relates to host bridges in computer systems.
II. Background Information
A typical computer system includes a host processor coupled to a host bridge. The host bridge interfaces the processor to, essentially, the rest of the computer system. The host bridge may be coupled to an input/output (I/O) bus such as a Peripheral Component Interconnect (PCI) bus. The host bridge may include a memory controller that is coupled to a system memory that may be a Dynamic Random Access Memory (DRAM). A PCI master device may be coupled to the PCI bus. The PCI master device may perform a read of a continuous stream of data using PCI read multiple semantics.
To sustain a PCI master read of a continuous stream (PCI read multiple semantics) to DRAM with minimal latency, the host bridge speculatively performs prefetching (or read ahead) of next sequentially addressed lines of data residing in the DRAM. The prefetched data from the DRAM is stored in a read data return holding buffer of the host bridge and is ready to be transferred to the PCI master at zero wait states. When the PCI master eventually disengages, the unused data, already prefetched to the holding buffer is to be discarded by the host bridge. In addition, for those prefetched lines of data that are still en-route to the holding buffer, the host bridge waits for data to return from the DRAM, and then proceeds to discard that data. This procedure, however, involves waiting for the unwanted data to be fetched and to return to the holding buffer, and then discarding that data. Accordingly, system memory bandwidth is wasted by the host bridge's unnecessary request of data from DRAM.
It is desirable to provide a mechanism that reduces unnecessary access to memory to avoid wasting precious memory bandwidth.